1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device, and particularly to a configuration of a semiconductor memory device operable in response to a rapidly applied external signal.
2. Description of the Background Art
Rapid operation of a semiconductor memory device requires rapid changes in the rising and falling of a signal externally input to the semiconductor memory device.
This results in setting high driving capability of a signal driver circuit of an external device which provides data to the semiconductor memory device.
However, the interconnections on the board where a semiconductor memory device is actually mounted equivalently have, for example, a parasitic, distributed inductance component. Accordingly, a larger change rate of an input signal relative to time causes a greater disturbance in waveform of the signal taken into the semiconductor memory device.
FIG. 12 shows how the waveform of an input signal changes with time in a semiconductor memory device. In the figure, the high level of the input signal is the level of a potential VIH and the low level of the input signal is the level of a potential VIL.
When the input signal starts to rise from a low level to a high level at time t1, the waveform of the signal taken into the semiconductor memory device exceeds potential level VIH and results in a so-called overshooting waveform, as described above.
When the input signal similarly falls from a high level to a low level at time t2, the waveform of the input signal has an undershoot due to a parasitic inductance component existing in an interconnection on the board.
However, the presence of such overshoot and undershoot in the waveform of an input signal causes unstable operation of the semiconductor memory device and also degrades the stability in operation of the exact system configured on the board where the semiconductor memory device is mounted.
Accordingly, the waveforms of input signals are shaped generally in semiconductor memory devices to suppress generation of the overshoot and undershoot of the input signals.
FIG. 13 is a circuit diagram showing a configuration of a clamp circuit 700 which is on-chip incorporated into semiconductor memory device, for shaping input waveforms.
In FIG. 13, an n-channel MOS transistor Q1 is provided between a signal line 704 transmitting a signal applied to an input pad 702 and a power supply potential Vdd. An n-channel MOS transistor Q2 is also provided between signal line 704 and a ground potential GND. The gate of n-channel MOS transistor Q1 is connected to signal line 704 and is in diode connection such that the direction from signal line 704 towards power supply potential Vdd is a forward direction.
Similarly, the gate of n-channel MOS transistor Q2 is coupled with ground potential GND and is in diode connection such that the direction from ground potential GND toward signal line 704 is a forward direction.
FIG. 14 is a cross section for illustrating a configuration in cross section of clamping circuit 700 shown in FIG. 13.
N-channel MOS transistors Q1 and Q2 are both provided in a p-type well 722 formed in the main surface of a p-type substrate 720.
P-type well 722 is biased to e.g. a substrate potential Vbb supplied from a substrate potential generating circuit (not shown) which receives an external power supply potential and a ground potential to generate a negative substrate potential.
With the configuration of clamp element 700 shown in FIGS. 13 and 14, n-channel MOS transistor Q1 is turned on when the level of an input signal is higher than a potential Vdd+Vth, wherein Vth represents a threshold voltage of n-channel MOS transistor Q1.
Meanwhile, the back bias of n-channel MOS transistor Q1 is potential Vbb and a potential Vsb between the substrate and the source of n-channel MOS transistor Q1 is thus Vsb=Vdd+.vertline.Vbb.vertline. in providing a clamping operation. Thus, n-channel MOS transistor will be affected by large substrate effect. Note that .vertline.Vbb.vertline. represents the absolute value of substrate potential Vbb.
Accordingly, when a threshold voltage Vth of n-channel MOS transistor is 0.8 V in the normal substrate bias state, the threshold voltage rises to e.g. a Vth of approximately 1.2 V due to a large substrate effect.
Thus, the configuration of clamp circuit 700 shown in FIGS. 13 and 14 has a disadvantage that clamping effect cannot be effectively provided.
Furthermore, the configuration shown in FIGS. 13 and 14 is disadvantageously less resistant to input surge, since the clamp elements are both formed of n-channel MOS transistors and the oxide films of the n-channel MOS transistors are destroyed by input surge. It is thus difficult to employ the configuration of clamp circuit 700 shown in FIGS. 13 and 14 in the devices practically used.
FIG. 15 is a circuit diagram showing a configuration of a clamp circuit 800 as another example of the clamp circuit which is on-chip incorporated into a semiconductor memory device.
Clamp circuit 800 has a p-channel MOS transistor Q3 provided between signal line 704 and power supply potential Vdd.
The gate of p-channel MOS transistor Q3 is coupled with power supply potential Vdd and is thus in diode connection such that the direction from signal line 704 toward power supply potential Vdd is a forward direction.
The remaining configuration is similar to the configuration of clamp circuit 700 shown in FIG. 13, and hence the identical portions are designated by the identical reference characters and the description thereof is not repeated.
FIG. 16 is a cross section for illustrating the configuration in cross section of clamping circuit 800 shown in FIG. 15.
P-channel MOS transistor Q3 is provided in an n-type well 820 formed in the main surface of p-type substrate 720, and n-channel MOS transistor Q2 is provided in a p-type well 822 provided adjacent to n-type well 820.
N-type well 820 is biased to power supply potential Vdd and p-type well 822 is biased to ground potential GND.
P-type substrate 720 is required to be biased to the ground potential due to following reason: for the configuration of clamp circuit 800 shown in FIG. 16, a p-type diffusion region 824 corresponding to the drain region of p-channel MOS transistor Q3 connected to the input signal line and n-type well 820 are forwardly biased when the potential level of an input signal reaches or exceeds Vdd+Vbi, wherein Vbi represents a forward threshold voltage of pn junction. Furthermore, since the substrate is of p-type, a pnp bipolar transistor configured of p-type diffusion region 824, n-type well 820 and p-type substrate 720 is turned on.
Thus, clamp current flows from p-type diffusion region 824 to p-type substrate 720. Accordingly, if p-type substrate 720 is supplied with potential from a substrate potential generating circuit (not shown), for example, the clamp current will flow into the substrate potential generating circuit.
The clamp current flowing into the substrate will cause a positive potential in the substrate. This will induce latch-up phenomenon in CMOS circuit, which is fatal to proper operation of DRAM.
P-type substrate 720 is thus required to be biased to ground potential GND.
Meanwhile, in operating as a clamp element, pn junction is advantageously greater in current absorbing ability than MOS transistor.
Accordingly, it can be said that the configuration of clamp circuit 800 is more desirable than that of clamp circuit 700 shown in FIG. 13 in that clamp circuit 800 further suppresses overshoots of input signals.
FIG. 17 is a circuit diagram showing a configuration of a clamp circuit 900 as still another example of the clamp circuit which is on-chip mounted in a semiconductor memory device.
In clamp circuit 900, a pn junction diode Q4 is connected between input signal line 704 and power supply potential Vdd such that the direction from signal line 704 toward power supply potential Vdd is a forward direction, and a pn junction diode Q5 is connected between ground potential GND and input signal line 704 such that the direction from ground potential GND toward input signal line 704 is a forward direction.
FIG. 18 is a cross section for illustrating the configuration in cross section of clamp circuit 900 shown in FIG. 17.
In FIG. 18, an n well 820 formed in a main surface of p-type substrate 720 is supplied with power supply potential Vdd.
Meanwhile a p well 922 provided adjacent to n well 920 is supplied with ground potential GND.
Input signal line 704 is connected to a p-type diffusion region 924 provided in a main surface of n-type well 920. Input signal line 704 is also connected to an n-type diffusion region 926 formed in a main surface of p-type well 922.
Such a configuration results in forward bias of p-type diffusion region 924 connected to the signal line and n well 920 when the potential level of an input signal reaches or exceeds potential Vdd+Vbi, as in clamp circuit 800 described with reference to FIG. 16. Since the substrate is also of p-type in this example, a pnp bipolar transistor configured of p-type diffusion region 924, n well 920 and p-type substrate 720 is turned on.
Thus, clamp current flows p-type diffusion region 924 to p-type substrate 720, as in the example shown in FIG. 16. That is, the p-type substrate in clamp circuit 900 shown in FIG. 18 must also be connected to ground potential GND.
In this example, the clamp element is a pn junction diode and is thus larger in current absorbing ability than MOS transistor. Furthermore, the use of a pn junction diode as a clamp element dispenses with oxide film and thus has an advantage that oxide film is not destroyed by input surge.
It is thus greatly advantageous to configure a clamp circuit by employing a pn junction diode.
FIG. 19 shows a configuration in cross section of a memory cell array portion in a semiconductor memory devices particularly in a dynamic random access memory (DRAM), and FIG. 20 is a plan view of the configuration of the memory cell array.
In FIG. 19, p-type well 740 is provided in a main surface of p-type substrate 720. A memory cell is arranged in p-type well 740.
In general, each memory cell is configured of a single n-channel MOS transistor 750 and a single memory cell capacitor (not shown).
N-channel MOS transistor 750 is referred to as an access transistors and opens and closes the connection between one electrode of the memory cell capacitor and a selected pair of bit lines.
P-type well 740 is fixed at a negative voltage Vbb lower than the ground potential to increase the threshold voltage of the access transistor and increase the holding time of electric charge stored in a memory cell.
P-type well 740 is also provided with an n-type MOS sense amplifier 752 which is responsive to the data read from a memory cell for amplifying the potential level of a pair of bit lines connected to the selected memory cell.
An n-type well 742 is provided adjacent to p-type well 740. Provided in n-type well 742 is a p-channel MOS type sense amplifier 754 which cooperates with n-channel type MOS sense amplifier 752 to amplify the potential level of a pair of bit lines in response to the data stored in a selected memory cell. The potential level of n-type well 742 is fixed at a power supply potential Vcc of the p-channel MOS type sense amplifier, wherein power supply potential Vcc represents an internal power supply potential down-converted from external power supply voltage Vdd by a voltage-down converter (not shown) mounted in the semiconductor memory device.
Another n-type well 744 is also provided adjacent to p-type well 740. Formed in n-type well 744 is a p-channel type MOS transistor 756 of the transistors which configure a word driver circuit for driving the potential level of a selected word line. In general, the high level output from a word driver for driving a word line is a level of voltage Vpp higher that of internal power supply voltage Vcc in order to avoid the effect of voltage drop caused by the access transistor. Voltage Vpp is generated from external power supply voltage Vdd by means of a booster circuit mounted in the semiconductor integrated circuit device.
N-type well 744 is thus fixed at the potential Vpp level.
Referring now to FIG. 20 the memory cell array is divided into a plurality of memory cell blocks, each provided with a band of sense amplifiers SAB. Each memory cell block is also provided with a band of word drivers WDB provided with the word driver circuits shown in FIG. 19 such that the band of word drivers WDB and the band of sense of amplifiers SAB intersect with each other.
FIG. 21 is a cross section of another example of a memory cell array configuration of a conventional DRAM.
The memory cell array shown in FIG. 21 is similar in plan configuration to the memory cell array shown in FIG. 20.
In the configuration shown in FIG. 21 also, n-channel MOS transistor 750 included in a memory cell, n-channel MOS sense amplifier 752 configuring a sense amplifier, and n-channel MOS transistor 758 configuring a word driver are provided in p-type well 740 formed in a main surface of p-type substrate 720.
P-type well 740 is fixed at a negative voltage Vbb lower than ground potential GND to increase the threshold voltage of the access transistor and increase the holding time of electric charge stored in the memory cell.
Provided adjacent to p-type well 740 is n-type well 742 within which p-channel MOS sense amplifier 754 configuring a sense amplifier is provided The potential level of n-type well 742 is fixed at internal power supply voltage Vcc.
The configuration shown in FIG. 21 is different from that shown in FIG. 19 in that the word driver circuit for driving a word line is constituted only by n-channel MOS transistor 758.
Thus, a circuit of so-called self-boost type is applied as the word driver in the configuration shown in FIG. 21.
Accordingly in driving the potential level of a word line in the configuration shown in FIG. 21, the word driver circuit requires the sequence of providing a precharge operation followed by a boost operation.
As a result, it disadvantageously takes longer time to activate a word line and access speed is thus delayed, as compared with the configuration shown in FIG. 19.
In both FIGS. 19 and 21 also, the potential level of the p-type substrate is held at the potential level of the p-type well, i.e., substrate potential Vbb.
Accordingly, use of clamping circuits 800 and 900 shown in FIGS. 15 to 18 in DRAMs with the configurations shown in FIGS. 19 and 21 entails the following disadvantage: in both clamp circuit 800 in FIG. 15 and clamp circuit 900 in FIG. 17, the potential level of the p-type substrate need be ground potential GND. By contrast, in both of the configurations shown in FIGS. 19 and 21, the potential level of the p-type substrate must be substrate potential Vbb. Accordingly, the exact clamp circuits 800 and 900 cannot be applied to the DRAM shown in FIG. 19 or 21.
Such a disadvantage can be solved by employing a configuration of a DRAM which has a cross sectional configuration as shown in FIG. 22.
The DRAM in FIG. 22 is different in cross sectional configuration from that shown in FIG. 19 as follows.
More specifically, in the configuration of the DRAM shown in FIG. 22, p-type well 740 is electrically isolated from p-type substrate 720 by the introduction of a triple n-type well 746.
In other words, the configuration shown in FIG. 22 allows the potential level of p-type well 740 to be held at substrate potential Vbb, the potential level of n-type well 744 to be held at boosted potential Vpp, and the potential level of the p-type substrate to be set at the ground potential.
The configuration shown in FIG. 22, however, entails the following disadvantage.
More specifically, the configuration shown in FIG. 22 needs an n-type well 748 provided between p-type well 740 and n-type well 742 and adjacent to p-type well 740 so that p-type well 740 is completely surrounded by an n-type well.
Thus, n-type well 744, triple n-type well 746 and n-type well 748 completely surround p-type well 740 and the potential level thereof is held at boosted potential Vpp.
Meanwhile, the potential level of n-type well 742 provided with p-channel MOS sense amplifier 754 need be held at internal power supply potential Vcc and accordingly an isolation band 780 need be provided between n-type wells 748 and 742.
The provision of such an isolation band will, however, increase the area of the memory cell array and hence chip area if a plurality of bands of sense amplifiers are provided in the memory cell array, as shown in FIG. 20.
The potential level of p-type well 740 can also be set at substrate potential Vbb and the potential level of the p-type substrate can be set at ground potential GND by, for example, fixing the potential level of triple n-type well 746 to Vcc.
In this example, p-type well 740 need be completely surrounded by triple well 746, n-type well 748 and a new n-type well provided between n-type well 744 and p-type well 740 so that it is electrically isolated from the p-type substrate.
In this example, an isolation band is required between n-type well 744 provided with p-channel MOS transistor 756 configuring a word driver and the new n-type well provided to surround p-type well 740.
Accordingly, the area of the memory cell array and hence chip area will also be increased in this example if a plurality of word drivers are provided in the memory cell array, as shown in FIG. 20.